[cgl_discussion] Project Review: MCA Handler
venkatesh.pallipadi at intel.com
Tue Oct 29 10:54:46 PST 2002
No. Only userspace MCA decoder that I know of is at
But, as far as I know, it doesn't decode MISC registers. It only decodes the
MCA STATUS register values.
from IA32 spec on MCA MISC registers:
MISC registers are architecturally defined register, provided to contain
miscellaneous machine check control and status information. Implemented in
P4 at this point.
IA32_MCG_MISC MSR has only one bit (bit 0) defined to contain some
additional status information and rest 63 bits are reserved.
There are per bank IA32_MCi_MISC registers, which _may_ contain useful
information depending on MISCV bit of IA32_MCi_STATUS register.
My understanding is, as of now, STATUS registers contain most of the
information about the MCA error and there is very little additional
information in MISC registers. However, in future, we may need to change the
kernel MCA handler and/or user level MCA information decoder, as and when
the specification defines more information encoding for the MISC registers.
Please let me now if I am missing anything here.
From: Randy.Dunlap [mailto:rddunlap at osdl.org]
Sent: Friday, October 25, 2002 10:20 PM
To: Pallipadi, Venkatesh
Cc: 'cgl_discussion at lists.osdl.org'
Subject: RE: [cgl_discussion] Project Review: MCA Handler
I certainly agree that decoding the (MCE) registers in userspace
is preferable. Do you have anything that does that?
Specifically the MISC register(s)? Where is it available?
On Fri, 25 Oct 2002, Pallipadi, Venkatesh wrote:
| Hi Randy,
| Current MCA handler does decode the STATUS information during an MCA error
| and gives some generic error details (like TLB error, cache error etc) to
| the user. But we feel that providing the complete error information
| (decoding of MISC, ADDR and looking at whether this happened in one
| particular CPU or all the CPUs, etc) can be done better by a user tool or
| event log manager rather than in the kernel. We are logging the contents
| all the MCA related registers (including MISC register) at the time of an
| MCA error, which can then be used by the user level MCA error information
| -----Original Message-----
| From: Randy.Dunlap [mailto:rddunlap at osdl.org]
| Sent: Tuesday, October 22, 2002 5:16 PM
| To: Pallipadi, Venkatesh
| Cc: 'cgl_discussion at lists.osdl.org'
| Subject: Re: [cgl_discussion] Project Review: MCA Handler
| On Thu, 3 Oct 2002, Pallipadi, Venkatesh wrote:
| | Requirements related to MCA Handler project
| | -------------------------------------------
| | Requirement: 4.5 Platform Signal Handler
| | How MCA Handler meets the CGL requirements
| | ------------------------------------------
| | This patch adds the MCA error info. onto the event log, in the format
| | specified by PSH - Event log interface spec.
| | Project design information
| | --------------------------
| | This project adds a kernel patch to:
| | 1) Log the MCA errors onto event log as per the format defined in
| | Log spec.
| | 2) Add the support for logging the additional information available
| | an MCA in P4 based system.
| | Code location
| | -------------
| | The kernel patch for MCA Handler is located in the cgl development tree
| | under kernel/linux-2.4.18/patches/mca_log
| | _______________________________________________
| Hi Venkatesh,
| For Pentium 4, I think that you could add some real value to MCE reporting
| by decoding the MISC register bits to provide some useful information
| to users or whoever is trying to support a system after an MCE
| event occurs. How about it?
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