[cgl_discussion] Question for TEMs/ISVs/OEMs regarding pthread requirements

[Pradeep Kathail]

Instructions are called 

  LL - Load linked
  SC - Store Conditional

Typically these are used in a loop, to take care of higher priority 
process or other CPUs accessing the same data. Typical instruction 
sequence looks like:

  For Attomic increment, instruction sequence will look like:

L1:
  LL    reg, <address>
  ADD   reg, 1
  ## You can do more instructions here.
  SC   reg, <address>
  BEQ  L1
  NOP

Brgds.
Pradeep

At 1/31/2003 10:11 PM -0600, Corey Minyard wrote:
>Pradeep Kathail wrote:
>
>>At 1/31/2003 04:57 PM -0600, Corey Minyard wrote:
>> 
>>
>>>You cannot correctly implement it without changing userland.  Sorry, it just can't be done.  With the current NPTL and NGPT implementation, you end up with a window where the mutex is locked but the owner is unknown (in fact I'm not sure if the owner is ever known).  If another process comes along in that timeframe, it won't be able to do the priority boosting, and it's not like it can just wait for a little while for the other process to finally identify itself, that would kind of defeat the purpose of the whole thing :-).
>>>
>>>Also, I don't think it's possible to do the userland-only lock on a machine that doesn't have compare-and-swap (MIPS, ARM, and old x86s don't have it, for instance).    
>>
>>MIPS supports load/ store-conditional that can be used to implement
>>userland MUTEX.
>I had looked at the MIPS spec, and didn't notice that.  Thanks for the info.  I did find the test-and-set-bit instructions, but I didn't see anything that would compare-and-swap a whole word of data.  I'll look again.
>
>-Corey