[cgl_discussion] Question for TEMs/ISVs/OEMs regarding pthr ead requirements

[Hu, Boris]

ARM has a similar implementation. You could find the following code piece
from 
glibc/sysdeps/arm/atomicity.h

  static inline int  compare_and_swap (volatile long int *p, long int
oldval, long int newval)
  {
    int result, tmp;
    __asm__ ("\n"
             "0:\tldr\t%1,[%2]\n\t"
             "mov\t%0,#0\n\t"
             "cmp\t%1,%4\n\t"
             "bne\t1f\n\t"
             "swp\t%0,%3,[%2]\n\t"
             "cmp\t%1,%0\n\t"
             "swpne\t%1,%0,[%2]\n\t"
             "bne\t0b\n\t"
             "mov\t%0,#1\n"
             "1:"
             : "=&r" (result), "=&r" (tmp)
             : "r" (p), "r" (newval), "r" (oldval)
             : "cc", "memory");
    return result;
 }

boris

> -----Original Message-----
> From: Corey Minyard [mailto:cminyard at mvista.com]
> Sent: 2003?2?3? 12:10
> To: Pradeep Kathail
> Cc: Perez-Gonzalez, Inaky; george anzinger; cgl discussion; 
> Chen, Terence; Abbas, Mohamed
> Subject: Re: [cgl_discussion] Question for TEMs/ISVs/OEMs 
> regarding pthread requirements
> 
> 
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> Yes, I looked and found that.  Thank you.  I must have looked 
> at the ARM 
> spec twice and not at the MIPS spec, or something, since it 
> seems pretty 
> clear now.  This is similar to PPC, so I understand the concept.
> 
> - -Corey
> 
> Pradeep Kathail wrote:
> 
> |Instructions are called
> |
> |  LL - Load linked
> |  SC - Store Conditional
> |
> |Typically these are used in a loop, to take care of higher priority
> |process or other CPUs accessing the same data. Typical instruction
> |sequence looks like:
> |
> |  For Attomic increment, instruction sequence will look like:
> |
> |L1:
> |  LL    reg, <address>
> |  ADD   reg, 1
> |  ## You can do more instructions here.
> |  SC   reg, <address>
> |  BEQ  L1
> |  NOP
> |
> |Brgds.
> |Pradeep
> |
> |At 1/31/2003 10:11 PM -0600, Corey Minyard wrote:
> |
> |>Pradeep Kathail wrote:
> |>
> |>>At 1/31/2003 04:57 PM -0600, Corey Minyard wrote:
> |>>
> |>>
> |>>>You cannot correctly implement it without changing 
> userland.  Sorry, 
> it just can't be done.  With the current NPTL and NGPT 
> implementation, 
> you end up with a window where the mutex is locked but the owner is 
> unknown (in fact I'm not sure if the owner is ever known).  
> If another 
> process comes along in that timeframe, it won't be able to do the 
> priority boosting, and it's not like it can just wait for a 
> little while 
> for the other process to finally identify itself, that would kind of 
> defeat the purpose of the whole thing :-).
> |>>>
> |>>>Also, I don't think it's possible to do the userland-only 
> lock on a 
> machine that doesn't have compare-and-swap (MIPS, ARM, and old x86s 
> don't have it, for instance).    
> |>>
> |>>MIPS supports load/ store-conditional that can be used to implement
> |>>userland MUTEX.
> |>
> |>I had looked at the MIPS spec, and didn't notice that.  
> Thanks for the 
> info.  I did find the test-and-set-bit instructions, but I didn't see 
> anything that would compare-and-swap a whole word of data.  
> I'll look again.
> |>
> |>-Corey
> |
> |
> |
> 
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