[PATCH v6 00/25] iommu: Shared Virtual Addressing for SMMUv3
jean-philippe at linaro.org
Mon May 4 15:09:26 UTC 2020
On Thu, Apr 30, 2020 at 02:18:16PM -0700, Jacob Pan wrote:
> On Thu, 30 Apr 2020 16:33:59 +0200
> Jean-Philippe Brucker <jean-philippe at linaro.org> wrote:
> > Shared Virtual Addressing (SVA) allows to share process page tables
> > with devices using the IOMMU, PASIDs and I/O page faults. Add SVA
> > support to the Arm SMMUv3 driver.
> > Since v5 :
> > * Added patches 1-3. Patch 1 adds a PASID field to mm_struct as
> > discussed in  and . This is also needed for Intel ENQCMD.
> > Patch 2 adds refcounts to IOASID and patch 3 adds a couple of helpers
> > to allocate the PASID.
> > * Dropped most of iommu-sva.c. After getting rid of io_mm following
> > review of v5, there wasn't enough generic code left to justify the
> > indirect branch overhead of io_mm_ops in the MMU notifiers. I ended
> > up with more glue than useful code, and couldn't find an easy way to
> > deal with domains in the SMMU driver (we keep PASID tables per domain,
> > while x86 keeps them per device). The direct approach in patch 17 is
> > nicer and a little easier to read. The SMMU driver only gained 160
> > lines, while iommu-sva lost 470 lines.
> > As a result I dropped the MMU notifier patch.
> > Jacob, one upside of this rework is that we now free ioasids in
> > blocking context, which might help with your addition of notifiers
> > to ioasid.c
> Thanks for the note. It does make notifier much easier, plus the
> refcount can alleviate the constraint on ordering.
> I guess we don't share mmu notifier code for now :)
I think it's more efficient for each IOMMU driver to at least implement
their own invalidate_range() callback and avoid indirect branches. For the
rest I couldn't find a lot of code to share, most of it is writing PASID
tables and invalidating. We can revisit later, as long as we agree on the
bind() API the implementations should be similar enough.
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