[PATCH v2] iommu/arm-smmu-v3: Don't reserve implementation defined register space

Robin Murphy robin.murphy at arm.com
Wed May 13 12:17:02 UTC 2020


On 2020-05-13 12:02 pm, Jean-Philippe Brucker wrote:
> Some SMMUv3 implementation embed the Perf Monitor Group Registers (PMCG)
> inside the first 64kB region of the SMMU. Since PMCG are managed by a
> separate driver, this layout causes resource reservation conflicts
> during boot.
> 
> To avoid this conflict, don't reserve the MMIO regions that are
> implementation defined. Although devm_ioremap_resource() still works on
> full pages under the hood, this way we benefit from resource conflict
> checks.

Reviewed-by: Robin Murphy <robin.murphy at arm.com>

Although in case there's any other cause to resend, a couple of nits below.

> Fixes: 7d839b4b9e00 ("perf/smmuv3: Add arm64 smmuv3 pmu driver")
> Signed-off-by: Jean-Philippe Brucker <jean-philippe at linaro.org>
> ---
> v1->v2: simplify following Robin's comments
> https://lore.kernel.org/linux-iommu/20200506174629.1504153-1-jean-philippe@linaro.org/
> ---
>   drivers/iommu/arm-smmu-v3.c | 35 +++++++++++++++++++++++++++++++----
>   1 file changed, 31 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index 82508730feb7a1..af21d24a09e888 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -171,6 +171,8 @@
>   #define ARM_SMMU_PRIQ_IRQ_CFG1		0xd8
>   #define ARM_SMMU_PRIQ_IRQ_CFG2		0xdc
>   
> +#define ARM_SMMU_REG_SZ			0xe00

Since it's not necessarily self-explanatory at a glance, might this 
deserve a comment to clarify that it's the start of the first IMP-DEF 
region in the register map, and all the architectural registers that we 
care about lie below it?

> +
>   /* Common MSI config fields */
>   #define MSI_CFG0_ADDR_MASK		GENMASK_ULL(51, 2)
>   #define MSI_CFG2_SH			GENMASK(5, 4)
> @@ -628,6 +630,7 @@ struct arm_smmu_strtab_cfg {
>   struct arm_smmu_device {
>   	struct device			*dev;
>   	void __iomem			*base;
> +	void __iomem			*page1;
>   
>   #define ARM_SMMU_FEAT_2_LVL_STRTAB	(1 << 0)
>   #define ARM_SMMU_FEAT_2_LVL_CDTAB	(1 << 1)
> @@ -733,9 +736,8 @@ static struct arm_smmu_option_prop arm_smmu_options[] = {
>   static inline void __iomem *arm_smmu_page1_fixup(unsigned long offset,
>   						 struct arm_smmu_device *smmu)
>   {
> -	if ((offset > SZ_64K) &&
> -	    (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY))
> -		offset -= SZ_64K;
> +	if (offset > SZ_64K)
> +		return smmu->page1 + offset - SZ_64K;
>   
>   	return smmu->base + offset;
>   }
> @@ -4021,6 +4023,18 @@ err_reset_pci_ops: __maybe_unused;
>   	return err;
>   }
>   
> +static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t start,
> +				      resource_size_t size)
> +{
> +	struct resource res = {
> +		.flags = IORESOURCE_MEM,
> +		.start = start,
> +		.end = start + size - 1,

There doesn't seem to be much point in pretending size is a variable 
argument; I'd have just encoded ARM_SMMU_REG_SZ directly here.

Thanks,
Robin.

> +	};
> +
> +	return devm_ioremap_resource(dev, &res);
> +}
> +
>   static int arm_smmu_device_probe(struct platform_device *pdev)
>   {
>   	int irq, ret;
> @@ -4056,10 +4070,23 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>   	}
>   	ioaddr = res->start;
>   
> -	smmu->base = devm_ioremap_resource(dev, res);
> +	/*
> +	 * Don't map the IMPLEMENTATION DEFINED regions, since they may contain
> +	 * the PMCG registers which are reserved by the PMU driver.
> +	 */
> +	smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ);
>   	if (IS_ERR(smmu->base))
>   		return PTR_ERR(smmu->base);
>   
> +	if (arm_smmu_resource_size(smmu) > SZ_64K) {
> +		smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K,
> +					       ARM_SMMU_REG_SZ);
> +		if (IS_ERR(smmu->page1))
> +			return PTR_ERR(smmu->page1);
> +	} else {
> +		smmu->page1 = smmu->base;
> +	}
> +
>   	/* Interrupt lines */
>   
>   	irq = platform_get_irq_byname_optional(pdev, "combined");
> 


More information about the iommu mailing list