[PATCH v7 13/24] iommu/arm-smmu-v3: Enable broadcast TLB maintenance
maz at kernel.org
Thu May 21 14:38:35 UTC 2020
On 2020-05-21 15:17, Will Deacon wrote:
> On Tue, May 19, 2020 at 07:54:51PM +0200, Jean-Philippe Brucker wrote:
>> The SMMUv3 can handle invalidation targeted at TLB entries with shared
>> ASIDs. If the implementation supports broadcast TLB maintenance,
>> enable it
>> and keep track of it in a feature bit. The SMMU will then be affected
>> inner-shareable TLB invalidations from other agents.
>> A major side-effect of this change is that stage-2 translation
>> are now affected by all invalidations by VMID. VMIDs are all shared
>> the only ways to prevent over-invalidation, since the stage-2 page
>> are not shared between CPU and SMMU, are to either disable BTM or
>> different VMIDs. This patch does not address the problem.
> This sounds like a potential performance issue, particularly as we
> stage-2 contexts via VFIO directly. Maybe we could reserve some portion
> VMID space for the SMMU? Marc, what do you reckon?
Certainly doable when we have 16bits VMIDs. With smaller VMID spaces
v8.0), this is a bit more difficult (we do have pretty large v8.0
around). How many VMID bits are we talking about?
Jazz is not dead. It just smells funny...
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