[Ksummit-discuss] [TECH TOPIC] asm-generic implementations of low-level synchronisation constructs
Will Deacon
will.deacon at arm.com
Thu May 8 15:13:31 UTC 2014
On Thu, May 08, 2014 at 03:27:34PM +0100, Peter Zijlstra wrote:
> On Thu, May 08, 2014 at 11:13:12AM +0200, Peter Zijlstra wrote:
> > ATOMIC_RET(ptr, __ret, stmt)
> > ({
> > typeof(*ptr) __new, __val;
> >
> > smp_mb__before_llsc();
> >
> > do {
> > __val = load_locked(ptr);
> > stmt;
> > } while (!store_conditional(ptr, __new));
> >
> > smp_mb__after_llsc();
> >
> > __ret;
> > })
>
> So the most common constraint (which you've confirmed is true for ARM as
> well) is that we should not have memory accesses in between an LL/SC.
Yup.
> Making sure GCC doesn't do any is tricky, the best I can come up with is
> tagging all variables with the register qualifier, like:
>
> ATOMIC_RET(ptr, __ret, stmt)
> ({
> register typeof(*ptr) __new, __val;
>
> smp_mb__before_llsc();
>
> do {
> __val = load_locked(ptr);
> stmt;
> } while (!store_conditional(ptr, __new));
>
> smp_mb__after_llsc();
>
> __ret;
> })
>
> Now, I'm not at all sure if register still means anything to GCC, but in
> the faint hope that it still sees it as a hint this might just work.
I just ran this past our compiler guys and they threw rocks at me. Even if
it happens to work today, I don't think we can rely on it tomorrow,
unfortunately.
I think that makes the case for extended the fine-grained atomics
implemented by each architecture, but it would still be great to have a way
to compose them.
Will
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