[Linux-kernel-mentees] [PATCH v4] PCI: Add support for LTR

[kernel test robot]

Hi Puranjay,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on pci/next]
[also build test WARNING on pm/linux-next v5.9-rc6 next-20200925]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Puranjay-Mohan/PCI-Add-support-for-LTR/20200926-020527
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: microblaze-randconfig-r005-20200925 (attached as .config)
compiler: microblaze-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/8d07a88c56c747b6c2217cad501d3b0d5cfe8ca6
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Puranjay-Mohan/PCI-Add-support-for-LTR/20200926-020527
        git checkout 8d07a88c56c747b6c2217cad501d3b0d5cfe8ca6
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=microblaze 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>

All warnings (new ones prefixed by >>):

>> drivers/pci/pci.c:3064:5: warning: no previous prototype for 'pci_ltr_decode' [-Wmissing-prototypes]
    3064 | u64 pci_ltr_decode(u16 latency)
         |     ^~~~~~~~~~~~~~
>> drivers/pci/pci.c:3084:5: warning: no previous prototype for 'pci_ltr_encode' [-Wmissing-prototypes]
    3084 | u16 pci_ltr_encode(u64 val)
         |     ^~~~~~~~~~~~~~

vim +/pci_ltr_decode +3064 drivers/pci/pci.c

  3059	
  3060	/**
  3061	 * pci_ltr_decode - Decode the latency to a value in ns
  3062	 * @latency: latency according to PCIe base specification 7.8.2.
  3063	 */
> 3064	u64 pci_ltr_decode(u16 latency)
  3065	{
  3066		u16 scale = (latency & PCI_LTR_SCALE_MASK) >> 10;
  3067		u16 value = latency & PCI_LTR_VALUE_MASK;
  3068	
  3069		switch (scale) {
  3070		case 0: return value;
  3071		case 1: return value * 32;
  3072		case 2: return value * 1024;
  3073		case 3: return value * 32768;
  3074		case 4: return value * 1048576;
  3075		case 5: return value * 33554432;
  3076		}
  3077		return 0;
  3078	}
  3079	
  3080	/**
  3081	 * pci_ltr_encode - Encode the value in ns to a 16 bit register value
  3082	 * @val: latency according to PCIe base specification 7.8.2.
  3083	 */
> 3084	u16 pci_ltr_encode(u64 val)
  3085	{
  3086		if (val <= 1UL * 0x3ff)
  3087			return (0 << 10) | (val & 0x3ff);
  3088		if (val <= 32UL * 0x3ff)
  3089			return (1 << 10) | ((val >> 5) & 0x3ff);
  3090		if (val <= 1024UL * 0x3ff)
  3091			return (2 << 10) | ((val >> 10) & 0x3ff);
  3092		if (val <= 32768UL * 0x3ff)
  3093			return (3 << 10) | ((val >> 15) & 0x3ff);
  3094		if (val <= 1048576UL * 0x3ff)
  3095			return (4 << 10) | ((val >> 20) & 0x3ff);
  3096		if (val <= 33554432UL * 0x3ff)
  3097			return (5 << 10) | ((val >> 25) & 0x3ff);
  3098		return 0;
  3099	}
  3100	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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