[llvmlinux] AARCH64 unit tests for clang

Charlebois, Mark mcharleb at quicinc.com
Tue Oct 29 17:30:29 UTC 2013


Hi Tim,

Thanks so much for the insight, it was very helpful!

I have patches for the below and the latest clang/llvm did fix my t2.c issue with "%aN".

I have another asm issue that I hope you can provide insight on:

1. The following seems to generate 2 errors when compiled with clang with -O2 enabled, but works without -O2:

static inline void atomic_add(int i, atomic_t *v)
{
        unsigned long tmp;
        int result;

        __asm__ __volatile__("@ atomic_add\n"
"1:     ldxr    %w0, [%3]\n"
"       add     %w0, %w0, %w4\n"
"       stxr    %w1, %w0, [%3]\n"
"       cbnz    %w1, 1b"
        : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
        : "r" (&v->counter), "Ir" (i)
        : "cc");
}

/local2/mnt/workspace/llvmlinux/targets/vexpress64/src/linaro-aarch64/arch/arm64/include/asm/atomic.h:51:23: error: invalid
      operand in inline asm: '@ atomic_add
1:	ldxr	${0:w}, [$3]
	add	${0:w}, ${0:w}, ${4:w}
	stxr	${1:w}, ${0:w}, [$3]
	cbnz	${1:w}, 1b'
        __asm__ __volatile__("@ atomic_add\n"
                             ^
/local2/mnt/workspace/llvmlinux/targets/vexpress64/src/linaro-aarch64/arch/arm64/include/asm/atomic.h:51:23: error: invalid
      operand in inline asm: '@ atomic_add
1:	ldxr	${0:w}, [$3]
	add	${0:w}, ${0:w}, ${4:w}
	stxr	${1:w}, ${0:w}, [$3]
	cbnz	${1:w}, 1b'
4 warnings and 2 errors generated.

Thanks,

Mark
 
________________________________________
From: llvmlinux-bounces at lists.linuxfoundation.org [llvmlinux-bounces at lists.linuxfoundation.org] on behalf of Tim Northover [t.p.northover at gmail.com]
Sent: Tuesday, October 29, 2013 1:28 AM
To: Compiling the Linux Kernel with Clang/LLVM
Subject: Re: [llvmlinux] AARCH64 unit tests for clang

Hi Mark,

Just thought I'd add my perspective on these:

> 1. msr and mrs can pass a 32bit variable for gcc but it must be 64bit for
> clang

Tricky one. It doesn't seem to be an officially sanctioned alias
(though I may have missed that section), but you could certainly argue
it would be a good thing for some registers on convenience grounds.
You couldn't blindly add it as an alias for all of them, of course;
that would be very misleading.

> 2. prfm pldl1keep and prfm pstl1keep fail for clang

We didn't support the "%aN" operand modifier. Should be fixed in r193593.

> 3. The bfi instruction in the following code fails with the error indicated:

This is a worrying inconsistency in GCC: both ARM and x86 seem to
print the immediate token ('#' and '$' respectively) by default for
"i" constraints. There is a modifier 'c' which suppresses it:

    asm volatile("MY_INST %0, %c0" : : "i"(32))

produces just 'MY_INST #32, 32' on ARM and 'MY_INST $32, 32' on X86.
This is the approach Clang has taken in AArch64 (and Apple's ARM64,
incidentally). It would seem to be better if we could convince GCC
that they actually want some consistency.

AArch64 GCC doesn't support %cN currently, as an interim measure the
'#' isn't needed by GCC: both compilers should support "bfi %0, %1,
%2, #8".

Cheers.

Tim.
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